1. Field of the Invention
The present invention provides a method for forming an embedded memory MOS.
2. Description of the Prior Art
Due to continued process of integration, it is the present trend to produce semiconductor integrated circuits that simultaneously integrate a memory cell array and high-speed logic circuit elements onto a single chip. The result is the formation of an embedded memory which simultaneously combines a memory cell array and logic circuits, so as to save space and to enhance the speed of signal processing.
Please refer to FIG. 1 to FIG. 7. FIG. 1 to FIG. 7 are the cross-sectional schematic diagrams of making an embedded memory MOS on a semiconductor wafer 10 according to the prior art. The semiconductor wafer 10 comprises a silicon substrate 16, with a memory array area 12 and a periphery circuits region 14 defined on the surface of the silicon substrate 16. The memory array area 12 further comprises a single cell-well 13, and the periphery circuits region 14 further comprises a N-well 15 and a P-well 17. Each well is isolated by a plurality of shallow trench isolations 11.
As shown in FIG. 1, the method for forming an embedded memory MOS according to the prior art involves first depositing a silicon dioxide layer 18 and an undoped polysilicon layer 20, respectively, on the surface of a semiconductor wafer 10. Then, as shown in FIG. 2, a photoresist layer 22 is formed on the surface of the semiconductor wafer 10, followed by a photo process to define gate patterns of various PMOS and NMOS on the photoresist layer 22 in the periphery circuits region 14. Each gate pattern is subsequently used as a hard mask to etch the undoped polysilicon layer 20 down to the surface of the silicon dioxide layer 18, to form the gates 24 of both the PMOS and NMOS. Then, an ion implantation process is used to form lightly doped drains (LDD) 26 of each MOS.
After the complete removal of the photoresist layer 22 and the gate oxide layer 18 not covered by the gates 24, as shown in FIG. 3, a silicon nitride layer (not indicated) is formed on the surface of the semiconductor wafer 10, followed by an anisotropic etching process to form a spacer 28 located on either side of the gates 24 in the periphery circuits region 14. As shown in FIG. 4, two photo processes are used prior to ion implantation processes for two different ion implantation areas to form both a source 30 and a drain 32 for each PMOS and NMOS on top of each N well 17 and P well 15 in the periphery circuits region 14. At the same time, application of the ion implantation processes for the two different ion implantation areas lead to doping of the undoped polysilicon layer 20 of each gate 24 located on top of the P well 15 and N well 17.
As shown in FIG. 5, after completing the formation of the source 30 and drain 32 of each MOS in the periphery circuits region 14, a metal layer (not indicated) composed of Titanium(Ti) or Copper(Co) is sputtered on the surface of semiconductor wafer 10, followed by a first rapid thermal process (RTP) with a temperature range of 500xc2x0 C.xcx9c700xc2x0 C. and a heating duration of 10xcx9c30 seconds. Consequently, the Titanium atoms or Copper atoms in the metal layer diffuse into the surface of the undoped polysilicon layer 20 in the memory array area 12 and the surfaces of the source 30, drain 32 and gate 24 in the periphery circuits regions 14. Then, a wet etching process is performed to remove the unreacted metal layer on the surface of the semiconductor wafer 10. A second rapid thermal process (RTP) is used with a temperature range of 700xc2x0 C.xcx9c900xc2x0 C. and a heating duration of 10xcx9c30 seconds to form a self aligned metal silicide layer 34 on the surface of the undoped polysilicon layer 20 in the memory array area 12, as well as on the surfaces of the source 30, drain 32 and gate 24 in the periphery circuits area.
Thereafter, an insulator layer 36 composed of silicon nitride or silicon oxynitride (SiOxNy), is deposited on the semiconductor wafer 10, followed by a photo process to form a photoresist layer 38 on top of the insulator layer 36. As shown in FIG. 6, a photolithographic, exposure and development process is then performed to define a plurality of gate patterns in the photoresist layer 38 in the memory array area 12.
Finally as shown in FIG. 7, the gate patterns in the photoresist layer 38 is used as a hard mask to etch the insulator layer 36, the self aligned silicide layer 34, the undoped polysilicon layer 20, and the silicon dioxide layer 18 down to the surface of the silicon substrate 16 in order to form the gate 40 of each MOS in the memory array area 12.
The gate 40 in the memory array area 12 is required to have a cap layer 38 in order to make the successive self-aligned contact (SAC) process proceed smoothly. However, a cap layer cannot be formed on the surface of the gate 24 in the periphery circuits region 14. Thus, the surface sheet resistance (Rs) of each source 30, drain 32, and gate 34 in the successive self aligned silicide (salicide) process cannot be lowered. Therefore, in the prior art method for making the embedded memory MOS, repeated photolithographic and etching processes are needed in order to integrate the formation of gates in the memory array area and the periphery circuits region. The result is an increase in both the complexity of process and the production cost, as well as a reduction in throughput.
It is therefore a primary objective of the present invention to provide a method of forming an embedded memory MOS, so as to simultaneously form gates in the memory array area and the periphery circuits region so as to simplify the manufacturing process.
The method according to the present invention involves first forming a dielectric layer and an undoped polysilicon layer, respectively, on the surface of a semiconductor wafer with a defined memory array area and a periphery circuits region. Then, doping of the undoped polysilicon layer in the memory array area occurs to form a doped polysilicon layer. Thereafter, a protective layer is formed on the surface of the semiconductor wafer, followed by a first photolithographic and etching process (PEP) to define a plurality of gate patterns in the protective layer in the memory array area. Then, a second PEP is peformed to etch the undoped polysilicon layer in the periphery circuits region and the doped polysilicon layer in the memory array area to simultaneously form a gate of the MOS in both the periphery circuits region and the memory array area. Finally, a lightly doped drain (LDD) and a source/drain (S/D) of each MOS are formed adjacent to each gate, as well as a spacer formed on either side of each gate.
It is an advantage of the present invention that in the method for making the embedded memory MOS, the gate structures in both the memory array area and periphery circuits region can be simultaneously formed to decrease both process complexity and production cost.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment, which is illustrated in the various figures and drawings.